general description the ds1842 integrates the discrete high-voltage com- ponents necessary for avalanche photodiode (apd) bias and monitor applications. a switch fet is used in conjunction with an external dc-dc controller to create a boost dc-dc converter. a current clamp limits cur- rent through the apd and also features an external shutdown. the device also includes a dual current mir- ror to monitor the apd current. applications apd biasing gpon optical network unit and optical line transmission features ? 76v maximum boost voltage ? switch fet ? current monitor with a wide 1? to 2ma range, fast 50ns time constant, and 10:1 and 5:1 ratio ? 2ma current clamp with external shutdown ? multiple external filtering options ? 3mm x 3mm, 14-pin tdfn package with exposed pad ds1842 76v, apd, bias output stage with current monitoring ________________________________________________________________ maxim integrated products 1 ordering information 19-4557; rev 1; 3/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package ds1842n+ -40c to +85c 14 tdfn-ep* ds1842n+t&r -40c to +85c 14 tdfn-ep* pin configuration appears at end of data sheet. + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. ds1875 ds1842 sw fb d2 comp mon3 lx gate gnd mirin mir1 clamp mirout 3.3v current mirror current limit mir2 c bulk c comp r comp external monitor tia apd rosa typical application circuit
ds1842 76v, apd, bias output stage with current monitoring 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (t a = -40? to +85?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 2: rising mirout transition from 10? to 1ma; v mirin = 40v, 2.5k load. note 3: guaranteed by design; not production tested. voltage range on gate and clamp relative to gnd...................................................-0.3v to +12v voltage range on mirin, mirout, mir1, and mir2 relative to gnd........................-0.3v to +80v voltage range on lx relative to gnd...................-0.3v to +85v continuous power dissipation (t a = +70?) tdfn (derate 24.4mw/? above +70?).................1951.2mw operating junction temperature range ...........-40? to +150? storage temperature range .............................-55? to +135? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? package thermal characteristics (note 1) tdfn junction-to-ambient thermal resistance ( ja ) ............41?/w junction-to-case thermal resistance ( jc ) ...................8?/w parameter symbol conditions min typ max units switching frequency f sw 0 1.2 mhz c gate v gs = 0v, v ds = 25v 40 fet capacitance c lx f sw = 1mhz 90 pf fet gate resistance r g 22 v gs = 3v, i d = 170ma 4.6 10 fet on-resistance r dson v gs = 10v, i d = 170ma 3.7 8 gate voltage v gs 0 11 v switching current i lx duty cycle = 10%, f sw = 100khz 680 ma lx voltage v lx 80 v lx leakage i il(lx) v gate = 0v, v lx = 76v -1 +1 a clamp voltage v clamp 0 11 v clamp threshold v clt 2 4 7 v clamp = low 1.75 2.6 4 ma maximum mirout current i mirout clamp = high 10 a i mirout = 1ma 0.095 0.100 0.105 i mirout = 1a 0.094 0.100 0.106 mir1 to mirout ratio k mir1 15v < v mirin < 76v a/a i mirout = 1ma 0.190 0.200 0.210 i mirout = 1a 0.188 0.200 0.212 mir2 to mirout ratio k mir2 15v < v mirin < 76v a/a mir1, mir2 rise time (20%/80%) t rc (note 2) 30 ns shutdown temperature t shdn (note 3) +150 c leakage on gate and clamp i il -1 +1 a note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial .
ds1842 76v, apd, bias output stage with current monitoring _______________________________________________________________________________________ 3 mirin vs. mirout current (v mirin = 40v) ds1842 toc01 mirout current ( a) 1000 100 10 100 1000 10,000 10 1 10,000 mirin current vs. temperature (v mirin = 40v, i mirout = 250na) ds1842 toc02 temperature ( c) mirin current ( a) 80 60 20 40 0 -20 10 20 30 40 50 60 70 80 90 100 0 -40 100 mirin current vs. temperature (v mirin = 40v, i mirout = 2ma) ds1842 toc03 temperature ( c) mirin current (ma) 80 60 40 20 0 -20 1 2 3 4 5 0 -40 100 mir error vs. temperature (i mirout = 1 ds1842 toc04 temperature ( c) error (%) 80 60 40 20 0 -20 -1 0 1 2 -2 -40 100 mir1 mir2 mir error vs. temperature (i mirout = 1ma) ds1842 toc05 temperature ( c) error (%) 80 60 40 20 0 -20 -1 0 1 2 -2 -40 100 mir1 mir2 mir error vs. mirout current ds1842 toc06 mirout current ( mir error vs. mirin voltage ds1842 toc07 mirin voltage (v) error (%) 70 60 50 40 30 20 -1 0 1 2 -2 10 80 mir2 1 a mir2 1ma mir1 1 a mir1 1ma mirout clamp current vs. temperature ds1842 toc08 temperature ( c) i mirout (ma) 80 60 40 20 0 -20 1 2 3 4 5 0 -40 100 typical operating characteristics (t a = +25?, unless otherwise noted.)
ds1842 76v, apd, bias output stage with current monitoring 4 _______________________________________________________________________________________ typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) fet on-resistance vs. drain current ds1842 toc09 i ds (ma) r dson ( ) 100 10 4 5 6 7 3 1 1000 v gs = 2.5v v gs = 3.0v v gs = 3.6v v gs = 5v v gs = 10v fet drain current vs. drain voltage ds1842 toc10 drain voltage (v) i ds (ma) 3 2 1 100 200 300 400 500 600 700 0 04 v gs = 2.5v v gs = 3.0v v gs = 3.6v v gs = 5v v gs = 10v pin description pin name function 1 mir1 current mirror monitor output, 10:1 ratio 2 mir2 current mirror monitor output, 5:1 ratio 3 n.c. no connection. can be connected to gnd for compatibility with the ds1842a. 4, 9C12 n.c. no connection. not internally connected. 5 clamp clamp input. disables the current mirror output (mirout). 6 gate fet gate connection 7 gnd ground 8 lx fet drain connection. connect to switching inductor. 13 mirin current mirror input 14 mirout current mirror output. connect to apd bias pin. ep exposed pad. connect to ground. block diagram ds1842 lx gate gnd mirin mir1 clamp mirout current mirror current limit mir2 thermal shutdown
ds1842 76v, apd, bias output stage with current monitoring _______________________________________________________________________________________ 5 detailed description the ds1842 contains discrete high-voltage compo- nents required to create an apd bias voltage and to monitor the apd bias current. the device? mirror out- puts are a current that is a precise ratio of the output current across a large dynamic range. the mirror response time is fast enough to comply with gpon rx burst-mode monitoring requirements. the device has a built-in current-limiting feature to protect apds. the apd current can also be shut down by clamp or ther- mal shutdown. the internal fet is used in conjunction with a dc-dc boost controller to precisely create the apd bias voltage. current mirror the ds1842 has two current mirror outputs. one is a 10:1 mirror connected at mir1, and the other is a 5:1 mirror connected to mir2. the mirror output is typically connected to an adc using a resistor to convert the mirrored current into a voltage. the resistor to ground should be selected such that the maximum full-scale voltage of the adc is reached when the maximum mirrored current is reached. for example, if the maximum monitored cur- rent through the apd is 2ma with a 1v adc full scale, and the 10:1 mirror is used, then the correct resistor is approximately 5k . if both mir1 and mir2 are con- nected together, the correct resistor is 1.6k . the mirror response time is dominated by the amount of capacitance placed on the output. for burst-mode rx systems where the fastest response times are required (approximately a 50ns time constant), a 3.3pf capacitor and external op amp should be used to buffer the signal sent to the adc. for continuous mode applications, a 10nf capacitor is all that is required on the output. current clamp the ds1842 has a current clamping circuit to protect the apd by limiting the amount of current from mirout. there are three methods of current clamping available. 1) internally defined current limit the device? current clamp circuit automatically clamps the current when it exceeds i clamp . 2) external shutdown signal the clamp pin can completely shut down the current from mirout. the clamp pin is active high. 3) precise level set by external feedback circuit a feedback circuit is used to control the level applied to the clamp pin. figure 1 shows an example feedback circuit. thermal shutdown as a safety feature, the ds1842 has a thermal-shut- down circuit that turns off the mirout and mirin cur- rents when the internal die temperature exceeds t shdn . these currents resume after the device has cooled. switch fet and diode the ds1842 switching fet is designed to complement the ds1875 controller? built-in dc-dc boost controller. other dc-dc converters are also compatible, including the max1932. apd biasing of 16v to 76v can be achieved using the ds1842. clamp mir1 ref figure 1. current clamp from current feedback
ds1842 76v, apd, bias output stage with current monitoring 6 _______________________________________________________________________________________ tdfn top view 2 4 5 13 11 10 mirin n.c. n.c. mir2 n.c. clamp 1 14 mirout mir1 3 12 n.c. n.c. 6 9 n.c. gate 7 8 lx gnd ds1842 *ep *exposed pad. + pin configuration package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 14 tdfn-ep t1433+2 21-0137 90-0063
ds1842 76v, apd, bias output stage with current monitoring maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 _____________________ 7 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/09 initial release 1 3/11 updated the absolute maximum ratings section; added the package thermal characteristics section; changed pin 3 from gnd to n.c. in the pin description and pin configuration 2, 4, 6
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